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Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process.
Guangyi Lu
Yuan Wang
Lizhong Zhang
Jian Cao
Xing Zhang
Published in:
Sci. China Inf. Sci. (2016)
Keyphrases
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high speed
circuit design
data sets
case study
chip design
power consumption
computer aided
design decisions
power reduction
design process
low power
engineering design
power dissipation
electronic circuits
nm technology
analog circuits
cmos technology
user interface
artificial intelligence