Guangyi Lu

Publication Activity (10 Years)

Years Active: 2013-2023
Publications (10 Years): 12

Top Topics

Behavioral Model

Rotation Invariance

Top Venues

Sci. China Inf. Sci.

IEICE Electron. Express

Publications

Jiahao Wei, Weiqi Chen, Yajie Gong, Qi Wu, Guangyi Lu, Wei Gao, Lihui Wang, Mei Li, Haiming Wang
Highly Efficient Automatic Synthesis of a Millimeter-Wave On-Chip Deformable Spiral Inductor Using a Hybrid Knowledge-Guided and Data-Driven Technique. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (12) (2023)
Yize Wang, Guangyi Lu, Yuan Wang
A New Behavioral Model of Gate-Grounded NMOS for Simulating Snapback Characteristics. IEEE Access 8 (2020)
Guangyi Lu, Yuan Wang, Lizhong Zhang, Yize Wang, Ru Huang, Xing Zhang
Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity. ISCAS (2018)
Yuan Wang, Guangyi Lu, Yize Wang, Xing Zhang
Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness. IEICE Trans. Electron. (3) (2017)
Yize Wang, Yuan Wang, Guangyi Lu, Jian Cao, Xing Zhang
A novel TLP-based method to deliver IEC 61000-4-2 ESD stress. IEICE Electron. Express 14 (9) (2017)
Guangyi Lu, Yuan Wang, Yize Wang, Xing Zhang
Power-rail ESD clamp circuit with hybrid-detection enhanced triggering in a 65-nm, 1.2-V CMOS process. ISCAS (2017)
Guangyi Lu, Yuan Wang, Jian Cao, Song Jia, Xing Zhang
A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications. ISCAS (2016)
Jian Cao, Yize Wang, Yuan Wang, Guangyi Lu, Xing Zhang
A novel SPICE circuit model of electrostatic discharge (ESD) generator. IEICE Electron. Express 13 (9) (2016)
Guangyi Lu, Yuan Wang, Xing Zhang
Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process. IEICE Trans. Electron. (5) (2016)
Guangyi Lu, Yuan Wang, Lizhong Zhang, Jian Cao, Xing Zhang
Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process. Sci. China Inf. Sci. 59 (12) (2016)
Yuan Wang, Guangyi Lu, Haibing Guo, Jian Cao, Song Jia, Xing Zhang
Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process. Sci. China Inf. Sci. 59 (4) (2016)
Jian Cao, Jingya Xu, Yuan Wang, Guangyi Lu, Xing Zhang
A compact SCR model using advanced BJT models and standard SPICE elements. Sci. China Inf. Sci. 59 (10) (2016)
Guangyi Lu, Yuan Wang, Lizhong Zhang, Jian Cao, Song Jia, Xing Zhang
Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling. Sci. China Inf. Sci. 58 (4) (2015)
Jian Cao, Zhenxu Ye, Yuan Wang, Guangyi Lu, Xing Zhang
A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network. ASICON (2015)
Nan Han, Yuan Wang, Guangyi Lu, Jian Cao, Xing Zhang
Four-bit transient-to-digital converter with a single RC-based detection circuit for system-level ESD protection. ASICON (2015)
Guangyi Lu, Yuan Wang, Jian Cao, Song Jia, Ganggang Zhang, Xing Zhang
Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits. ASICON (2013)