Power-rail ESD clamp circuit with hybrid-detection enhanced triggering in a 65-nm, 1.2-V CMOS process.

Guangyi Lu Yuan Wang Yize Wang Xing Zhang

Published in: ISCAS (2017)

Keyphrases

high speed
detection method
detection algorithm
power consumption
power reduction
detection accuracy
silicon on insulator
anomaly detection
false alarms
object detection
automatic detection
duty cycle
image processing
detection rate
detection scheme
single phase