C
search
search
reviewers
reviewers
feeds
feeds
assignments
assignments
settings
logout
Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness.
Yuan Wang
Guangyi Lu
Yize Wang
Xing Zhang
Published in:
IEICE Trans. Electron. (2017)
Keyphrases
</>
high speed
power reduction
power consumption
single phase
shortest path
parallel implementation
neural network
control system
low cost
shared memory
parallel computing
communication channels
massively parallel
chip design