Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process.
Guangyi LuYuan WangXing ZhangPublished in: IEICE Trans. Electron. (2016)
Keyphrases
- cmos technology
- nm technology
- optimization strategy
- optimization strategies
- low power
- power consumption
- optimization algorithm
- high speed
- low cost
- global optimization
- parallel processing
- constrained optimization
- metal oxide semiconductor
- high density
- optimization method
- dynamic logic
- information security
- optimization process
- query optimization
- power dissipation
- particle swarm optimization
- programmable logic
- protection scheme
- evolutionary algorithm