A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations.
Kanglin XiaoXin QiaoXiaoxin CuiJiahao SongHaoyang LuoXin'an WangYuan WangPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2024)
Keyphrases
- random access memory
- knowledge base
- power reduction
- low power
- storage media
- power consumption
- dynamic random access memory
- memory requirements
- high dimensional
- cmos technology
- main memory
- sparse representation
- low cost
- hardware implementation
- data transmission
- processing elements
- leakage current
- embedded dram
- control system