A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation.
Kanglin XiaoXiaoxin CuiXin QiaoJiahao SongHaoyang LuoXin'an WangYuan WangPublished in: IEEE Trans. Circuits Syst. II Express Briefs (2023)