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A Computing-in-Memory SRAM Macro Based on Fully-Capacitive-Coupling With Hierarchical Capacity Attenuator for 4-b MAC Operation.
Kanglin Xiao
Xiaoxin Cui
Xin Qiao
Nanbing Pan
Xin'an Wang
Yuan Wang
Published in:
ISCAS (2022)
Keyphrases
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random access memory
memory capacity
memory space
power consumption
limited memory
hierarchical structure
main memory
neural network
high speed
memory requirements
coarse to fine
data transmission
computational power
memory usage