A Scan Matrix Design for Low Power Scan-Based Test.

Shih Ping Lin Chung-Len Lee Jwu E. Chen

Published in: Asian Test Symposium (2005)

Keyphrases

low power
single chip
power consumption
low power consumption
high speed
low cost
vlsi architecture
logic circuits
gate array
digital signal processing
mixed signal
vlsi circuits
cmos technology
power dissipation
design considerations
power reduction
high power
nm technology
multi channel