An On-Chip Jitter Measurement Circuit for the PLL.

Chin-Cheng Tsai Chung-Len Lee

Published in: Asian Test Symposium (2003)

Keyphrases

analog vlsi
high speed
circuit design
evolvable hardware
cmos technology
chip design
micron cmos
data acquisition
low power
power dissipation
high density
low cost
digital circuits
analog circuits
evolutionary algorithm
power reduction
packet loss
single chip
printed circuit boards
quality of service
neural network