A cell-based power estimation in CMOS combinational circuits.
Jiing-Yuan LinTai-Chien LiuWen-Zen ShenPublished in: ICCAD (1994)
Keyphrases
- power consumption
- power dissipation
- logic circuits
- delay insensitive
- low power
- chip design
- high speed
- analog vlsi
- circuit design
- asynchronous circuits
- cmos technology
- power reduction
- vlsi circuits
- accurate estimation
- low cost
- low voltage
- neural network
- floating gate
- robust estimation
- estimation algorithm
- parameter estimation
- focal plane
- estimation error
- analog circuits
- estimation process
- estimation accuracy
- density estimation
- image processing