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An automorphic approach to verification pattern generation for SoC design verification using port-order fault model.

Chun-Yao WangShing-Wu TungJing-Yang Jou
Published in: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2002)
Keyphrases
  • pattern generation
  • functional verification
  • fault model
  • formal verification
  • model checking
  • formal methods
  • case study
  • low cost
  • knowledge based systems
  • signature verification
  • image quality
  • design process