Shing-Wu Tung

Publication Activity (10 Years)

Years Active: 1998-2013
Publications (10 Years): 0

Top Topics

Design Considerations

Top Venues

Publications

Wei-Xiang Tang, Shui-An Wen, Shing-Wu Tung, Keng-Yu Lin, Chun-Chih Chen, Ching-Lung Su
A 42.5µW/MHz ultra-low power 32-bit microcontroller - SPARK. ICICS (2013)
Hsien-Ching Hsieh, Shr-Je Lin, Chun-Nan Liu, Jen-Chieh Yeh, Shing-Wu Tung, Ding-Ming Kwai
A case study: 3-D stacked memory system architecture exploration by ESL virtual platform. VLSI-DAT (2013)
Shui-An Wen, Chun-Chin Chen, Shing-Wu Tung
A power management technology for mobile embedded system. VLSI-DAT (2012)
Po-Han Huang, Chi-Hung Lin, Hsien-Ching Hsieh, Huang-Lun Lin, Shing-Wu Tung
Low power and high performance 3-D multimedia platform. Hot Chips Symposium (2012)
Jen-Chieh Yeh, Kung-Ming Ji, Shing-Wu Tung, Shau-Yin Tseng
Heterogeneous Multi-core SoC Implementation with System-Level Design Methodology. HPCC (2011)
Hsien-Ching Hsieh, Shui-An Wen, Che-Yu Liao, Huang-Lun Lin, Po-Han Huang, Shing-Wu Tung
Low power design and dynamic power management system for VLIW DSP subsystem. ISPACS (2011)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
SoC design integration by using automatic interconnection rectification. ISCAS (4) (2003)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
Automatic interconnection rectification for SoC design verification based on the port order fault model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (1) (2003)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
An automatic interconnection rectification technique for SoC design integration. ASP-DAC (2003)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
On automatic-verification pattern generation for SoC withport-order fault model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (4) (2002)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
An automorphic approach to verification pattern generation for SoC design verification using port-order fault model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21 (10) (2002)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
An Improved AVPG Algorithm for SoC Design Verification Using Port Order Fault Model. Asian Test Symposium (2001)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
An AVPG for SOC design verification with port order fault model. ISCAS (5) (2001)
Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
On generation of the minimum pattern set for data path elements in SoC design verification based on port order fault model. HLDVT (2001)
Chih-Yuan Chen, Shing-Wu Tung
ELITE Design Methodology of Foundation IP for Improving Synthesis Quality. ISQED (2001)
Shing-Wu Tung, Jing-Yang Jou
A Logical Fault Model for Library Coherence Checking. J. Inf. Sci. Eng. 14 (3) (1998)
Shing-Wu Tung, Jing-Yang Jou
Verification Pattern Generation for Core-Based Design Using Port Order Fault Model. Asian Test Symposium (1998)