Hsien-Ching Hsieh

Publication Activity (10 Years)

Years Active: 2011-2014
Publications (10 Years): 0

Top Topics

Layered Architecture

Top Venues

ACM Great Lakes Symposium on VLSI

Publications

Hsien-Ching Hsieh, Yi-Fa Sun, Jen-Chieh Yeh, Po-Han Huang
3-D stacked memory system architecture exploration by esl virtual platform and reconfigurable stacking memory architecture in 3D-DSP SoC system. ICASSP (2014)
Po-Han Huang, Huang-Lun Lin, Hsien-Ching Hsieh, Chi-Hung Lin, Shui-An Wen, Yi-Fa Sun
Low power 3-D stacking multimedia platform with reconfigurable memory architecture. ACM Great Lakes Symposium on VLSI (2013)
Hsien-Ching Hsieh, Shr-Je Lin, Chun-Nan Liu, Jen-Chieh Yeh, Shing-Wu Tung, Ding-Ming Kwai
A case study: 3-D stacked memory system architecture exploration by ESL virtual platform. VLSI-DAT (2013)
Chang-Hsin Cheng, Hsien-Ching Hsieh, Tso-Yi Fan, Wei-Xiang Tang, Chung-Kai Liu, Po-Han Huang
High resolution and frame rate image signal processor array design for 3-D imager. ISPACS (2012)
Po-Han Huang, Chi-Hung Lin, Hsien-Ching Hsieh, Huang-Lun Lin, Shing-Wu Tung
Low power and high performance 3-D multimedia platform. Hot Chips Symposium (2012)
Yi-Fa Sun, Chun-Nan Liu, Tse-Min Chen, Hsien-Ching Hsieh, Jen-Chieh Yeh, Yung-Chang Chang
Improvement of Multimedia Performance Based on 3-D Stacking Memory Architecture and Software Refinement. HPCC-ICESS (2012)
Hsien-Ching Hsieh, Po-Han Huang, Chi-Hung Lin, Huang-Lun Lin
Stacking memory architecture exploration for three-dimensional integrated circuit in 3-D PAC. SoCC (2012)
Chi-Hung Lin, Wen-Tsan Hsieh, Hsien-Ching Hsieh, Chun-Nan Liu, Jen-Chieh Yeh
System-level design exploration for 3-D stacked memory architectures. CODES+ISSS (2011)
Hsien-Ching Hsieh, Shui-An Wen, Che-Yu Liao, Huang-Lun Lin, Po-Han Huang, Shing-Wu Tung
Low power design and dynamic power management system for VLIW DSP subsystem. ISPACS (2011)