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RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction.
Shang-Wei Tu
Yao-Wen Chang
Jing-Yang Jou
Published in:
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. (2006)
Keyphrases
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high speed
low cost
phase locked loop
simulation environment
encoding scheme
low power
complexity reduction