Kai-Yuan Chao

Publication Activity (10 Years)

Years Active: 1994-2024
Publications (10 Years): 5

Top Topics

Destination Node

Distributed Heterogeneous

Advanced Technology

Optimization Procedure

Top Venues

ACM Great Lakes Symposium on VLSI

Publications

Yu Zhang, Yuan Pu, Fangzhou Liu, Peiyu Liao, Kai-Yuan Chao, Keren Zhu, Yibo Lin, Bei Yu
Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells. ISPD (2024)
Zhen Zhuang, Kai-Yuan Chao, Bei Yu, Tsung-Yi Ho, Martin D. F. Wong
Multi-Product Optimization for 3D Heterogeneous Integration with D2W Bonding. ICCAD (2023)
Zhen Zhuang, Bei Yu, Kai-Yuan Chao, Tsung-Yi Ho
Multi-Package Co-Design for Chiplet Integration. ICCAD (2022)
Genggeng Liu, Xinghai Zhang, Wenzhong Guo, Xing Huang, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang
Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (6) (2022)
Szu-Yuan Han, Wen-Hao Liu, Rickard Ewetz, Cheng-Kok Koh, Kai-Yuan Chao, Ting-Chi Wang
Delay-driven layer assignment for advanced technology nodes. ASP-DAC (2017)
Rickard Ewetz, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang, Cheng-Kok Koh
A study on the use of parallel wiring techniques for sub-20nm designs. ACM Great Lakes Symposium on VLSI (2014)
Xin-Wei Shih, Tzu-Hsuan Hsu, Hsu-Chieh Lee, Yao-Wen Chang, Kai-Yuan Chao
Symmetrical buffered clock-tree synthesis with supply-voltage alignment. ASP-DAC (2013)
Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao
NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32 (5) (2013)
Shih-Lien Lu, Tanay Karnik, Ganapati Srinivasa, Kai-Yuan Chao, Doug Carmean, Jim Held
Scaling the "Memory Wall": Designer track. ICCAD (2012)
Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng
A Practical Low-Power Nonregular Interconnect Design With Manufacturing for Design Approach. IEEE J. Emerg. Sel. Topics Circuits Syst. 2 (2) (2012)
Yuelin Du, Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao
Hybrid lithography optimization with E-Beam and immersion processes for 16nm 1D gridded design. ASP-DAC (2012)
Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao
Lithography-aware layout modification considering performance impact. ISQED (2011)
Shing-Tung Lin, Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao
Simultaneous redundant via insertion and line end extension for yield optimization. ASP-DAC (2011)
Wen-Hao Liu, Yih-Lang Li, Kai-Yuan Chao
High-quality global routing for multiple dynamic supply voltage designs. ICCAD (2011)
Hongbo Zhang, Yuelin Du, Martin D. F. Wong, Kai-Yuan Chao
Mask cost reduction with circuit performance consideration for self-aligned double patterning. ASP-DAC (2011)
Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao
Multi-threaded collision-aware global routing with bounded-length maze routing. DAC (2010)
Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao
On process-aware 1-D standard cell design. ASP-DAC (2010)
Kuang-Yao Lee, Ting-Chi Wang, Cheng-Kok Koh, Kai-Yuan Chao
Optimal Double Via Insertion With On-Track Preference. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29 (2) (2010)
Qiang Ma, Martin D. F. Wong, Kai-Yuan Chao
Configurable multi-product floorplanning. ASP-DAC (2010)
Zhe-Wei Jiang, Meng-Kai Hsu, Yao-Wen Chang, Kai-Yuan Chao
Spare-cell-aware multilevel analytical placement. DAC (2009)
Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao, Liang Deng
Wire shaping is practical. ISPD (2009)
Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao
Fast and Optimal Redundant Via Insertion. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (12) (2008)
Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao
Optimal post-routing redundant via insertion. ISPD (2008)
Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong
Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (4) (2008)
Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong
Fast Dummy-Fill Density Analysis With Coupling Constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27 (4) (2008)
Liang Deng, Martin D. F. Wong, Kai-Yuan Chao, Hua Xiang
Coupling-aware Dummy Metal Insertion for Lithography. ASP-DAC (2007)
Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong
Dummy fill density analysis with coupling constraints. ISPD (2007)
Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong
Is your layout density verification exact?: a fast exact algorithm for density calculation. ISPD (2007)
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
An ECO routing algorithm for eliminating coupling-capacitance violations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (9) (2006)
Kuang-Yao Lee, Ting-Chi Wang, Kai-Yuan Chao
Post-routing redundant via insertion and line end extension with via density consideration. ICCAD (2006)
Hua Xiang, Kai-Yuan Chao, Martin D. F. Wong
Exact Algorithms for Coupling Capacitance Minimization by Adding One Metal Layer. ISQED (2005)
Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao
Simultaneous floor plan and buffer-block optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (5) (2004)
Hua Xiang, Kai-Yuan Chao, D. F. Wong
An ECO algorithm for eliminating crosstalk violations. ISPD (2004)
Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou, Kai-Yuan Chao
Simultaneous floorplanning and buffer block planning. ASP-DAC (2003)
Ruibing Lu, Guoan Zhong, Cheng-Kok Koh, Kai-Yuan Chao
Flip-Flop and Repeater Insertion for Early Interconnect Planning. DATE (2002)
Hua Xiang, Kai-Yuan Chao, D. F. Wong
ECO algorithms for removing overlaps between power rails and signal wires. ICCAD (2002)
Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong
Minimum Crosstalk Vertical Layer Assignment for Three-Layer VHV Channel Routing. VLSI Design 1998 (1) (1998)
Kai-Yuan Chao, D. F. Wong
Signal integrity optimization on the pad assignment for high-speed VLSI design. ICCAD (1995)
Shashidhar Thakur, Kai-Yuan Chao, D. F. Wong
An Optimal Layer Assignment Algorithm for Minimizing Crosstalk for Three Layer VHV Channel Routing. ISCAS (1995)
Kai-Yuan Chao, D. F. Wong
Floorplanning for Low Power Designs. ISCAS (1995)
Kai-Yuan Chao, D. F. Wong
Thermal placement for high-performance multichip modules. ICCD (1995)
Kai-Yuan Chao, D. F. Wong
Layer assignment for high-performance multi-chip modules. ICCAD (1994)