Cache Capacity Aware Thread Scheduling for Irregular Memory Access on many-core GPGPUs.
Hsien-Kai KuoTa-Kan YenBo-Cheng Charles LaiJing-Yang JouPublished in: ASP-DAC (2013)
Keyphrases
- memory access
- data access
- main memory
- memory hierarchy
- cache misses
- access latency
- external memory
- shared memory
- memory management
- scheduling problem
- processing units
- scheduling algorithm
- high volume
- data storage
- access patterns
- data management
- parallel machines
- data structure
- memory bandwidth
- multiprocessor systems
- databases
- memory space
- secondary storage
- graphical models
- data model
- database systems
- website