RLC effects on worst-case switching pattern for on-chip buses.

Shang-Wei Tu Jing-Yang Jou Yao-Wen Chang

Published in: ISCAS (2) (2004)

Keyphrases

worst case
pattern matching
high density
lower bound
upper bound
low cost
average case
greedy algorithm
np hard
running times
public transport
analog vlsi
data sets
error bounds
single chip