Two-level logic minimization for low power.
Jyh-Mou TsengJing-Yang JouPublished in: ACM Trans. Design Autom. Electr. Syst. (1999)
Keyphrases
- low power
- logic circuits
- low cost
- power consumption
- high speed
- delay insensitive
- single chip
- wireless transmission
- high power
- image sensor
- digital signal processing
- vlsi architecture
- gate array
- vlsi circuits
- cmos technology
- power reduction
- mixed signal
- asynchronous circuits
- real time
- low power consumption
- signal processing