Yen-Lung Chen

Publication Activity (10 Years)

Years Active: 2010-2024
Publications (10 Years): 8

Top Topics

Simultaneous Optimization

Image Deblurring

Analog Circuits

Fully Integrated

Top Venues

IEEE J. Solid State Circuits

Publications

Po-Shao Chen, Yen-Lung Chen, Yu-Chi Lee, Zih-Sing Fu, Chia-Hsiang Yang
A 28.8-mW Accelerator IC for Dark Channel Prior-Based Blind Image Deblurring. IEEE J. Solid State Circuits 59 (6) (2024)
Yen-Lung Chen, Chung-Hsuan Yang, Yi-Chung Wu, Chao-Hsi Lee, Wen-Ching Chen, Liang-Yi Lin, Nian-Shyang Chang, Chun-Pin Lin, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang
A Fully Integrated End-to-End Genome Analysis Accelerator for Next-Generation Sequencing. ISSCC (2023)
Chung-Hsuan Yang, Yi-Chung Wu, Yen-Lung Chen, Chao-Hsi Lee, Jui-Hung Hung, Chia-Hsiang Yang
An FM-Index Based High-Throughput Memory-Efficient FPGA Accelerator for Paired-End Short-Read Mapping. IEEE Trans. Biomed. Circuits Syst. 17 (6) (2023)
Yen-Lung Chen, Bo-Yi Chang, Chia-Hsiang Yang, Tzi-Dar Chiueh
A High-Throughput FPGA Accelerator for Short-Read Mapping of the Whole Human Genome. IEEE Trans. Parallel Distributed Syst. 32 (6) (2021)
Po-Shao Chen, Yen-Lung Chen, Yu-Chi Lee, Fu Zih-Sing, Chia-Hsiang Yang
A 28.8mW Accelerator IC for Dark Channel Prior Based Blind Image Deblurring. A-SSCC (2021)
Yi-Chung Wu, Yen-Lung Chen, Chung-Hsuan Yang, Chao-Hsi Lee, Chao-Yang Yu, Nian-Shyang Chang, Ling-Chien Chen, Jia-Rong Chang, Chun-Pin Lin, Hung-Lieh Chen, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang
A 975-mW Fully Integrated Genetic Variant Discovery System-on-Chip in 28 nm for Next-Generation Sequencing. IEEE J. Solid State Circuits 56 (1) (2021)
Yi-Chung Wu, Yen-Lung Chen, Chung-Hsuan Yang, Chao-Hsi Lee, Chao-Yang Yu, Nian-Shyang Chang, Ling-Chien Chen, Jia-Rong Chang, Chun-Pin Lin, Hung-Lieh Chen, Chi-Shi Chen, Jui-Hung Hung, Chia-Hsiang Yang
21.1 A Fully Integrated Genetic Variant Discovery SoC for Next-Generation Sequencing. ISSCC (2020)
Wei Wu, Yen-Lung Chen, Yue Ma, Chien-Nan Jimmy Liu, Jing-Yang Jou, Sudhakar Pamarti, Lei He
Wave digital filter based analog circuit emulation on FPGA. ISCAS (2016)
Hsin-Ju Chang, Yen-Lung Chen, Conan Yeh, Chien-Nan Jimmy Liu
Layout-aware analog synthesis environment with yield consideration. ISQED (2015)
Wei Wu, Peng Gu, Yen-Lung Chen, Chien-Nan Liu, Sudhakar Pamarti, Chang Wu, Lei He
Toward Wave Digital Filter based Analog Circuit Emulation on FPGA (Abstract Only). FPGA (2015)
Yen-Lung Chen, Wei Wu, Chien-Nan Jimmy Liu, Lei He
Incremental Latin hypercube sampling for lifetime stochastic behavioral modeling of analog circuits. ASP-DAC (2015)
Yung-Yue Chen, Yen-Lung Chen, Bo-Hui Zhou
Robust guidance law design for UAVs. ICCA (2014)
Yen-Lung Chen, Guan-Ming Chu, Ying-Chi Lien, Ching-Mao Lee, Chien-Nan Jimmy Liu
Simultaneous optimization for low dropout regulator and its error amplifier with process variation. VLSI-DAT (2014)
Yen-Lung Chen, Wan-Rong Wu, Chien-Nan Jimmy Liu, James Chien-Mo Li
Simultaneous Optimization of Analog Circuits With Reliability and Variability for Applications on Flexible Electronics. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33 (1) (2014)
Wei Wu, Wenyao Xu, Rahul Krishnan, Yen-Lung Chen, Lei He
REscope: High-dimensional Statistical Circuit Simulation towards Full Failure Region Coverage. DAC (2014)
Yu-Ching Liao, Yen-Lung Chen, Xian-Ting Cai, Chien-Nan Jimmy Liu, Tai-Chen Chen
LASER: layout-aware analog synthesis environment on laker. ACM Great Lakes Symposium on VLSI (2013)
Yen-Lung Chen, Wan-Rong Wu, Guan-Ruei Lu, Chien-Nan Jimmy Liu
Automatic circuit sizing technique for the analog circuits with flexible TFTs considering process variation and bending effects. DATE (2013)
Yen-Lung Chen, Yi-Ching Ding, Yu-Ching Liao, Hsin-Ju Chang, Chien-Nan Jimmy Liu
A layout-aware automatic sizing approach for retargeting analog integrated circuits. VLSI-DAT (2013)
Chien-Nan Jimmy Liu, Yen-Lung Chen, Chin-Cheng Kuo, I-Ching Tsai
A fast heuristic approach for parametric yield enhancement of analog designs. ACM Trans. Design Autom. Electr. Syst. 17 (3) (2012)
Chin-Cheng Kuo, Yen-Lung Chen, I-Ching Tsai, Li-Yu Chan, Chien-Nan Jimmy Liu
Behavior-level yield enhancement approach for large-scaled analog circuits. DAC (2010)