Abhishek Patyal

Publication Activity (10 Years)

Years Active: 2018-2023
Publications (10 Years): 9

Top Topics

Principal Component Analysis

Hierarchical Agglomerative Clustering

Top Venues

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.

Publications

Abhishek Patyal, Hung-Ming Chen, Mark Po-Hung Lin, Guan-Qi Fang, Simon Yi-Hung Chen
Pole-Aware Analog Layout Synthesis Considering Monotonic Current Flows and Wire Crossings. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (1) (2023)
A. K. Thasreefa, Abhishek Patyal, Hao-Yu Chi, Mark Po-Hung Lin, Hung-Ming Chen
On Reducing LDE Variations in Modern Analog Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42 (4) (2023)
K. A. Asha, Li En Hsu, Abhishek Patyal, Hung-Ming Chen
Improving the Quality of FPGA RO-PUF by Principal Component Analysis (PCA). ACM J. Emerg. Technol. Comput. Syst. 17 (3) (2021)
Abhishek Patyal, Po-Cheng Pan, K. A. Asha, Hung-Ming Chen, Wei-Zen Chen
Exploring Multiple Analog Placements With Partial-Monotonic Current Paths and Symmetry Constraints Using PCP-SP. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39 (12) (2020)
Abhishek Patyal, Hung-Ming Chen, Mark Po-Hung Lin
Late Breaking Results: Pole-aware Analog Placement Considering Monotonic Current Flow and Crossing-Wire Minimization. DAC (2020)
Mark Po-Hung Lin, Hao-Yu Chi, Abhishek Patyal, Zheng-Yao Liu, Jun-Jie Zhao, Chien-Nan Jimmy Liu, Hung-Ming Chen
Achieving Analog Layout Integrity through Learning and Migration Invited Talk. ICCAD (2020)
Po-Cheng Pan, Hung-Wen Huang, Chien-Chia Huang, Abhishek Patyal, Hung-Ming Chen, Tsun-Yu Yang
On Closing the Gap Between Pre-Simulation and Post-Simulation Results in Nanometer Analog Layouts. SMACD (2018)
K. A. Asha, Abhishek Patyal, Hung-Ming Chen
Generation of PUF-Keys on FPGAs by K-means Frequency Clustering. AsianHOST (2018)
Abhishek Patyal, Po-Cheng Pan, K. A. Asha, Hung-Ming Chen, Hao-Yu Chi, Chien-Nan Liu
Analog placement with current flow and symmetry constraints using PCP-SP. DAC (2018)