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Using power gating techniques in area-array SoC floorplan design.

Chi-Yi YehHung-Ming ChenLi-Da HuangWei-Ting WeiChao-Hung LuChien-Nan Jimmy Liu
Published in: SoCC (2007)
Keyphrases
  • computer aided
  • design process
  • design decisions
  • design issues
  • user interface
  • low cost
  • hardware and software
  • design space
  • chip design