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Using power gating techniques in area-array SoC floorplan design.
Chi-Yi Yeh
Hung-Ming Chen
Li-Da Huang
Wei-Ting Wei
Chao-Hung Lu
Chien-Nan Jimmy Liu
Published in:
SoCC (2007)
Keyphrases
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computer aided
design process
design decisions
design issues
user interface
low cost
hardware and software
design space
chip design