Li-Da Huang

Publication Activity (10 Years)

Years Active: 2002-2009
Publications (10 Years): 0

Publications

Bo-Zhou Chen, Hung-Ming Chen, Li-Da Huang, Po-Cheng Pan
A stochastic-based efficient critical area extractor on OpenAccess platform. ACM Great Lakes Symposium on VLSI (2009)
Lun-Chun Wei, Hung-Ming Chen, Li-Da Huang, Sarah Songjie Xu
Efficient and optimal post-layout double-cut via insertion by network relaxation and min-cost maximum flow. ACM Great Lakes Symposium on VLSI (2008)
Hua Xiang, Liang Deng, Li-Da Huang, Martin D. F. Wong
OPC-Friendly Bus Driven Floorplanning. ISQED (2007)
Chi-Yi Yeh, Hung-Ming Chen, Li-Da Huang, Wei-Ting Wei, Chao-Hung Lu, Chien-Nan Jimmy Liu
Using power gating techniques in area-array SoC floorplan design. SoCC (2007)
Gang Xu, Li-Da Huang, David Z. Pan, Martin D. F. Wong
Redundant-via enhanced maze routing for yield improvement. ASP-DAC (2005)
Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong
Simultaneous power supply planning and noise avoidance in floorplan design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (4) (2005)
Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. ICCD (2004)
Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu
A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (1) (2004)
Li-Da Huang, Martin D. F. Wong
Optical proximity correction (OPC): friendly maze routing. DAC (2004)
Li-Da Huang, Minghorng Lai, Martin D. F. Wong, Youxin Gao
Maze routing with buffer insertion under transition time constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22 (1) (2003)
Hung-Ming Chen, Li-Da Huang, I-Min Liu, Minghorng Lai, D. F. Wong
Floorplanning with power supply noise avoidance. ASP-DAC (2003)
Muzhou Shao, Martin D. F. Wong, Huijing Cao, Youxin Gao, Li-Pen Yuan, Li-Da Huang, Seokjin Lee
Explicit gate delay model for timing evaluation. ISPD (2003)
Li-Da Huang, Hung-Ming Chen, D. F. Wong
Global Wire Bus Configuration with Minimum Delay Uncertainty. DATE (2003)
Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. DATE (2002)
Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao
Maze Routing with Buffer Insertion under Transition Time Constraints. DATE (2002)