I-Min Liu

Publication Activity (10 Years)

Years Active: 1999-2010
Publications (10 Years): 0

Publications

Fang-Yu Fan, Hung-Ming Chen, I-Min Liu
Technology mapping with crosstalk noise avoidance. ASP-DAC (2010)
Huaizhi Wu, Martin D. F. Wong, I-Min Liu, Yusu Wang
Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26 (7) (2007)
Huaizhi Wu, Martin D. F. Wong, I-Min Liu
Timing-constrained and voltage-island-aware voltage assignment. DAC (2006)
Hung-Ming Chen, I-Min Liu, Martin D. F. Wong
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25 (11) (2006)
Hung-Ming Chen, Li-Da Huang, I-Min Liu, Martin D. F. Wong
Simultaneous power supply planning and noise avoidance in floorplan design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24 (4) (2005)
Hua Xiang, I-Min Liu, Martin D. F. Wong
Wire Planning with Bounded Over-the-Block Wires. ISQED (2005)
Huaizhi Wu, I-Min Liu, Martin D. F. Wong, Yusu Wang
Post-placement voltage island generation under performance requirement. ICCAD (2005)
Hung-Ming Chen, I-Min Liu, Martin D. F. Wong, Muzhou Shao, Li-Da Huang
I/O Clustering in Design Cost and Performance Optimization for Flip-Chip Design. ICCD (2004)
Li-Da Huang, Xiaoping Tang, Hua Xiang, Martin D. F. Wong, I-Min Liu
A polynomial time-optimal diode insertion/routing algorithm for fixing antenna problem [IC layout]. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23 (1) (2004)
Hung-Ming Chen, Li-Da Huang, I-Min Liu, Minghorng Lai, D. F. Wong
Floorplanning with power supply noise avoidance. ASP-DAC (2003)
Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, I-Min Liu
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem. DATE (2002)
I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong
Integrated power supply planning and floorplanning. ASP-DAC (2001)
I-Min Liu, Adnan Aziz, D. F. Wong
Meeting Delay Constraints in DSM by Minimal Repeater Insertion. DATE (2000)
I-Min Liu, Adnan Aziz
Delay Constrained Optimization by Simultaneous Fanout Tree Construction, Buffer Insertion/Sizing and Gate Sizing. ICCD (2000)
I-Min Liu, Tan-Li Chou, Adnan Aziz, D. F. Wong
Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion. ISPD (2000)
Hai Zhou, Martin D. F. Wong, I-Min Liu, Adnan Aziz
Simultaneous routing and buffer insertion with restrictions onbuffer locations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19 (7) (2000)
I-Min Liu, Adnan Aziz, D. F. Wong, Hai Zhou
An Efficient Buffer Insertion Algorithm for Large Networks Based on Lagrangian Relaxation. ICCD (1999)
Hai Zhou, D. F. Wong, I-Min Liu, Adnan Aziz
Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. DAC (1999)