A 65nm low power 2T1D embedded DRAM with leakage current reduction.

Mu-Tien Chang Po-Tsang Huang Wei Hwang

Published in: SoCC (2007)

Keyphrases

cmos technology
low power
low voltage
leakage current
embedded dram
power consumption

random access memory
low cost
high speed
power reduction
power line
dynamic random access memory

digital signal processing
single chip
low power consumption
power dissipation
image sensor

nm technology
energy efficiency
silicon on insulator
digital images
image processing