Mu-Tien Chang

Publication Activity (10 Years)

Years Active: 2007-2018
Publications (10 Years): 4

Top Topics

Massive Datasets

Memory Management

Top Venues

IEEE Trans. Computers

Publications

Mu-Tien Chang, I. Stephen Choi, Dimin Niu, Hongzhong Zheng
Performance Impact of Emerging Memory Technologies on Big Data Applications: A Latency-Programmable System Emulation Approach. ACM Great Lakes Symposium on VLSI (2018)
Tyler Stocksdale, Mu-Tien Chang, Hongzhong Zheng, Frank Mueller
Architecting HBM as a high bandwidth, high capacity, self-managed last-level cache. PDSW-DISCS@SC (2017)
Krishna T. Malladi, Mu-Tien Chang, Dimin Niu, Hongzhong Zheng
FlashStorageSim: Performance Modeling for SSD Architectures. NAS (2017)
Ishwar Bhati, Mu-Tien Chang, Zeshan Chishti, Shih-Lien Lu, Bruce L. Jacob
DRAM Refresh Mechanisms, Penalties, and Trade-Offs. IEEE Trans. Computers 65 (1) (2016)
Krishna T. Malladi, Mu-Tien Chang, John Ping, Hongzhong Zheng
FAME: A Fast and Accurate Memory Emulator for New Memory System Architecture Exploration. MASCOTS (2015)
Mu-Tien Chang, Paul Rosenfeld, Shih-Lien Lu, Bruce L. Jacob
Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM. HPCA (2013)
Mu-Tien Chang, Joe Gross, Bruce L. Jacob
Energy-Efficient Cached DIMM Architecture. MASCOTS (2012)
Mu-Tien Chang, Bruce L. Jacob
An analytical model to estimate PCM failure probability due to process variations. SoCC (2011)
Mu-Tien Chang, Wei Hwang
A fully-differential subthreshold SRAM cell with auto-compensation. APCCAS (2008)
Mu-Tien Chang, Po-Tsang Huang, Wei Hwang
A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. SoCC (2008)
Mu-Tien Chang, Po-Tsang Huang, Wei Hwang
A 65nm low power 2T1D embedded DRAM with leakage current reduction. SoCC (2007)