Zuow-Zun Chen

Publication Activity (10 Years)

Years Active: 2010-2017
Publications (10 Years): 8

Top Topics

Cmos Technology

Top Venues

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Zuow-Zun Chen, Yen-Cheng Kuan, Yilei Li, Boyu Hu, Chien-Heng Wong, Mau-Chung Frank Chang
DPLL for Phase Noise Cancellation in Ring Oscillator-Based Quadrature Receivers. IEEE J. Solid State Circuits 52 (4) (2017)
Zuow-Zun Chen, Yilei Li, Yen-Cheng Kuan, Boyu Hu, Chien-Heng Wong, Mau-Chung Frank Chang
Digital PLL for phase noise cancellation in ring oscillator-based I/Q receivers. VLSI Circuits (2016)
Yan Zhao, Zuow-Zun Chen, Yuan Du, Yilei Li, Richard Al Hadi, Gabriel Virbila, Yinuo Xu, Yanghyo Kim, Adrian Tang, Theodore Reck, Mau-Chung Frank Chang
A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology. IEEE J. Solid State Circuits 51 (12) (2016)
Yuan Du, Wei-Han Cho, Yilei Li, Chien-Heng Wong, Jieqiong Du, Po-Tsang Huang, Yanghyo Kim, Zuow-Zun Chen, Sheau Jiung Lee, Mau-Chung Frank Chang
A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS. VLSI Circuits (2016)
Yan Zhao, Zuow-Zun Chen, Gabriel Virbila, Yinuo Xu, Richard Al Hadi, Yanghyo Kim, Adrian Tang, Theodore Reck, Huan-Neng Ron Chen, Chewnpu Jou, Fu-Lung Hsueh, Mau-Chung Frank Chang
2.1 An integrated 0.56THz frequency synthesizer with 21GHz locking range and -74dBc/Hz phase noise at 1MHz offset in 65nm CMOS. ISSCC (2016)
Boyu Hu, Fengbo Ren, Zuow-Zun Chen, Xicheng Jiang, Mau-Chung Frank Chang
An 8-Bit Compressive Sensing ADC With 4-GS/s Equivalent Speed Utilizing Self-Timed Pipeline SAR-Binary-Search. IEEE Trans. Circuits Syst. II Express Briefs (10) (2016)
Li Du, Yan Zhang, Frank Hsiao, Adrian Tang, Yan Zhao, Yilei Li, Zuow-Zun Chen, Liting Huang, Mau-Chung Frank Chang
6.7 A 2.3mW 11cm-range bootstrapped and correlated-double-sampling (BCDS) 3D touch sensor for mobile devices. ISSCC (2015)
Zuow-Zun Chen, Yen-Hsiang Wang, Jaewook Shin, Yan Zhao, Seyed Arash Mirhaj, Yen-Cheng Kuan, Huan-Neng Ron Chen, Chewnpu Jou, Ming-Hsien Tsai, Fu-Lung Hsueh, Mau-Chung Frank Chang
14.9 Sub-sampling all-digital fractional-N frequency synthesizer with -111dBc/Hz in-band phase noise and an FOM of -242dB. ISSCC (2015)
Zuow-Zun Chen, Tai-Cheng Lee
The Design and Analysis of Dual-Delay-Path Ring Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2011)
Zuow-Zun Chen, Tai-Cheng Lee
The Study of a Dual-Mode Ring Oscillator. IEEE Trans. Circuits Syst. II Express Briefs (4) (2011)
Kevin Fong, Yu-Cheng Hung, Zuow-Zun Chen, Tai-Cheng Lee
An all-digital de-skew clock generator for arbitrary wide range delay. APCCAS (2010)