Tai-Cheng Lee

Publication Activity (10 Years)

Years Active: 2000-2024
Publications (10 Years): 27

Top Topics

Synthetic Aperture Radar Images

Top Venues

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Hao-Hsuan Chang, Ci-Ren Chen, Tai-Cheng Lee
A 511-μW 89-dB-SNDR Asynchronous SAR-ISDM ADC With Noise Shaping Dynamic Amplifier and Time-Domain Noise-Slicing Technique. IEEE J. Solid State Circuits 59 (7) (2024)
Yu-Hong Yang, Mou Tzou, Tai-Cheng Lee
A 6.0-11.0 Gb/s Reference-Less Sub-Baud-Rate Linear CDR With Wide-Range Frequency Acquisition Technique. IEEE Trans. Circuits Syst. II Express Briefs 70 (2) (2023)
Yen-Chun Chan, Che-Wei Chang, Tai-Cheng Lee
A 0.9-V 50-MS/s 67.3-dB-SNDR SAR-ISDM ADC With an Oscillator-Based Integrator. IEEE Trans. Circuits Syst. II Express Briefs 70 (9) (2023)
Cheng-Tang Chen, Yu-Hong Yang, Tai-Cheng Lee
A Type-3 FMCW Radar Synthesizer with Wide Frequency Modulation Bandwidth. ISCAS (2022)
Yen-Po Lai, Hao-Hsuan Chang, Tai-Cheng Lee
An Asynchronous Zero-Crossing-Based Incremental Delta-Sigma Converter. VLSI-DAT (2022)
Hao-Hsuan Chang, Tung-Cheng Lin, Tai-Cheng Lee
A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier. IEEE Trans. Circuits Syst. II Express Briefs 69 (4) (2022)
Po-Yan Chen, Bing-Ting Ke, Tai-Cheng Lee, I-Ching Tsai, Tai-Wei Kung, Li-Yi Lin, En-Cheng Liu, Yun-Chih Chang, Yih-Lang Li, Mango C.-T. Chao
A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction. ISPD (2022)
Li-Wei Chen, Yao-Nien Sui, Tai-Cheng Lee, Yih-Lang Li, Mango C.-T. Chao, I-Ching Tsai, Tai-Wei Kung, En-Cheng Liu, Yun-Chih Chang
Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration Designs. ISQED (2022)
Tai-Cheng Lee, Cheng-Yen Yang, Yih-Lang Li
/TPlace: Machine Learning-Based Delay-Aware Transistor Placement for Standard Cell Synthesis. ICCAD (2020)
Hsiang-Chun Cheng, Yu-Hong Yang, Tai-Cheng Lee
Analysis and Design of a Self-Charged Crystal Oscillator with Pulse Regulating Feedback Loop. VLSI-DAT (2020)
Hsiu-Hsien Ting, Tai-Cheng Lee
25.6 A 5.25GHz Subsampling PLL with a VCO-Phase-Noise Suppression Technique. ISSCC (2020)
Kun-Ruei Li, Wei-Sung Chang, Tai-Cheng Lee
A 5 GHz Outer-Loop Phase Noise Filter with Delay-Sampling Technique. ISCAS (2020)
Tai-Cheng Lee, Yih-Lang Li
Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell Delay. IEEE Trans. Very Large Scale Integr. Syst. 27 (10) (2019)
Yu-Lun Hsieh, Tai-Cheng Lee
A SAR-Assisted Continuous-Time Incremental ΣΔ ADC With First-Order Noise Coupling. ASICON (2019)
Chin-Yu Lin, Yen-Hsin Wei, Tai-Cheng Lee
A 10-bit 2.6-GS/s Time-Interleaved SAR ADC With a Digital-Mixing Timing-Skew Calibration Technique. IEEE J. Solid State Circuits 53 (5) (2018)
Venkatesh Srinivasan, Stephane Le Tuai, Tai-Cheng Lee
F2: FinFETs & FDSOI - A mixed signal circuit designer's perspective. ISSCC (2018)
Jui-Cheng Hsiao, Dai-En Jhou, Tai-Cheng Lee
A 10-Gb/s equalizer with digital adaptation. ISOCC (2017)
Tai-Cheng Lee, Bob Verbruggen, Un-Ku Moon
Session 28 overview: Hybrid ADCs. ISSCC (2017)
Hsuan-Yun Kao, Cheng-Ting Tsai, Chun-Yen Pong, Shan-Fong Liang, Zu-Kai Weng, Yu-Chieh Chi, Hao-Chung Kuo, Jian Jang Huang, Tai-Cheng Lee, Tien-Tsorng Shih, Jau-Ji Jou, Wood-Hi Cheng, Chao-Hsin Wu, Gong-Ru Lin
Few-mode 850-nm VCSEL chip with direct 16-QAM OFDM encoding at 80-Gbit/s for 100-m OM4 MMF link. OFC (2017)
Wei-Sung Chang, Dai-En Jhou, Yu-Hong Yang, Tai-Cheng Lee
An energy-efficient self-charged crystal oscillator with a quadrature-phase shifter technique. A-SSCC (2017)
Wei-Sung Chang, Tai-Cheng Lee
A 5 GHz Fractional-N ADC-Based Digital Phase-Locked Loops With -243.8 dB FOM. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2016)
Chin-Yu Lin, Yen-Hsin Wei, Tai-Cheng Lee
27.7 A 10b 2.6GS/s time-interleaved SAR ADC with background timing-skew calibration. ISSCC (2016)
Chin-Yu Lin, Chien-Heng Wong, Chia-Hau Hsu, Yen-Hsin Wei, Tai-Cheng Lee
Noise. IEEE Trans. Circuits Syst. II Express Briefs (9) (2016)
Venkatesh Srinivasan, Tai-Cheng Lee
Session 15 overview: Oversampling data converters. ISSCC (2016)
Chin-Yu Lin, Tai-Cheng Lee
A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique. IEEE Trans. Circuits Syst. I Regul. Pap. (7) (2016)
Chun-Ping Wang, Tai-Cheng Lee
A technique for in-band phase noise reduction in fractional-N frequency synthesizers. A-SSCC (2016)
Chia-Lun Chang, Tai-Cheng Lee
A Compact Multi-Input Power Conversion System with High Time-Efficiency Inductor-Sharing Technique for Thermoelectric Energy Harvesting Applications. J. Circuits Syst. Comput. 25 (1) (2016)
Chen-Kai Hsu, Tai-Cheng Lee
A single-channel 10-b 400-MS/s 8.7-mW pipeline ADC in a 90-nm technology. A-SSCC (2015)
Ting-Yang Wang, Tai-Cheng Lee
A 84.7-DR wide BW incremental ADC using CT structure. VLSI-DAT (2015)
Cheng-Jyun Li, Tai-Cheng Lee
2.4-GHz High-Efficiency Adaptive Power. IEEE Trans. Very Large Scale Integr. Syst. 22 (2) (2014)
Chin-Yu Lin, Tai-Cheng Lee
A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique. VLSIC (2014)
Chia-Lun Chang, Tai-Cheng Lee
A compact multi-input thermoelectric energy harvesting system with 58.5% power conversion efficiency and 32.4-mW output power capability. ISIC (2014)
Li-Hung Chiueh, Tai-Cheng Lee
A 6-Gb/s adaptive-loop-bandwidth clock and data recovery (CDR) circuit. A-SSCC (2014)
Yu-Hsuan Kang, Chin-Yu Lin, Tai-Cheng Lee
A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator. ISCAS (2014)
Po-Chun Huang, Wei-Sung Chang, Tai-Cheng Lee
21.2 A 2.3GHz fractional-N dividerless phase-locked loop with -112dBc/Hz in-band phase noise. ISSCC (2014)
Jia-An Jheng, Wei-Sung Chang, Tai-Cheng Lee
A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth. VLSI-DAT (2014)
Wei-Sung Chang, Po-Chun Huang, Tai-Cheng Lee
A Fractional-N Divider-Less Phase-Locked Loop With a Subsampling Phase Detector. IEEE J. Solid State Circuits 49 (12) (2014)
Chin-Yu Lin, Yen-Chuan Huang, Tai-Cheng Lee
Analysis of the leakage effect in a pipelined ADC with nanoscale CMOS technologies. VLSI-DAT (2013)
Chin-Yu Lin, Tai-Cheng Lee
Jitter error cancellation technique in digital domain for ADC. VLSI-DAT (2013)
Chien-Heng Wong, Tai-Cheng Lee
A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator. IEEE Trans. Circuits Syst. I Regul. Pap. (5) (2013)
Chia-Chi Ho, Tai-Cheng Lee
A 10-bit 200-MS/s reconfigurable pipelined A/D converter. VLSI-DAT (2012)
Zuow-Zun Chen, Tai-Cheng Lee
The Design and Analysis of Dual-Delay-Path Ring Oscillators. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2011)
Yen-Chuan Huang, Tai-Cheng Lee
A 10-bit 100-MS/s 4.5-mW Pipelined ADC With a Time-Sharing Technique. IEEE Trans. Circuits Syst. I Regul. Pap. (6) (2011)
Zuow-Zun Chen, Tai-Cheng Lee
The Study of a Dual-Mode Ring Oscillator. IEEE Trans. Circuits Syst. II Express Briefs (4) (2011)
Yen-Chuan Huang, Tai-Cheng Lee
9-Bit 50-MS/s Cyclic ADC in 90-nm Digital CMOS Technology. IEEE J. Solid State Circuits 45 (3) (2010)
Tai-Cheng Lee, Cheng-Hsiao Lin
Nonlinear R-2R Transistor-Only DAC. IEEE Trans. Circuits Syst. I Regul. Pap. (10) (2010)
Kevin Fong, Yu-Cheng Hung, Zuow-Zun Chen, Tai-Cheng Lee
An all-digital de-skew clock generator for arbitrary wide range delay. APCCAS (2010)
Yen-Chuan Huang, Tai-Cheng Lee
A 10b 100MS/s 4.5mW pipelined ADC with a time sharing technique. ISSCC (2010)
Chin-Yu Lin, Chun-Yu Chiang, Tai-Cheng Lee
An offset phase-locked loop spread spectrum clock generator for SATA III. CICC (2010)
Li-Han Hung, Tai-Cheng Lee
A Split-Based Digital Background Calibration Technique in Pipelined ADCs. IEEE Trans. Circuits Syst. II Express Briefs (11) (2009)
Keng-Jan Hsiao, Tai-Cheng Lee
An 8-GHz to 10-GHz Distributed DLL for Multiphase Clock Generation. IEEE J. Solid State Circuits 44 (9) (2009)
Keng-Jan Hsiao, Tai-Cheng Lee
A Low-Jitter 8-to-10GHz Distributed DLL for Multiple-Phase Clock Generation. ISSCC (2008)
Keng-Jan Hsiao, Tai-Cheng Lee
The Design and Analysis of a Fully Integrated Multiplying DLL With Adaptive Current Tuning. IEEE J. Solid State Circuits 43 (6) (2008)
Hong-Sing Kao, Ming-Jen Yang, Tai-Cheng Lee
A Delay-Line-Based GFSK Demodulator for Low-IF Receivers. ISSCC (2007)
Ding-Lan Shen, Tai-Cheng Lee
A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers. IEEE J. Solid State Circuits 42 (2) (2007)
Tai-Cheng Lee, Chin-Chi Chen
A mixed-signal GFSK demodulator for Bluetooth. IEEE Trans. Circuits Syst. II Express Briefs (3) (2006)
Tai-Cheng Lee, Wei-Liang Lee
A Spur Suppression Technique for Phase-Locked Frequency Synthesizers. ISSCC (2006)
Tai-Cheng Lee, Keng-Jan Hsiao
The design and analysis of a DLL-based frequency synthesizer for UWB application. IEEE J. Solid State Circuits 41 (6) (2006)
Tai-Cheng Lee, Yen-Chuan Huang
The design and analysis of a Miller-divider-based clock generator for MBOA-UWB application. IEEE J. Solid State Circuits 41 (6) (2006)
Ding-Lan Shen, Tai-Cheng Lee
A linear-approximation technique for digitally-calibrated pipelined A/D converters. ISCAS (2) (2005)
Tai-Cheng Lee, Yen-Chuan Huang
An optimization technique for RF buffers with active inductors. ISCAS (4) (2005)
Hung-Chieh Tsai, Jyh-Yih Yeh, Wei-Hsuan Tu, Tai-Cheng Lee, Chorng-Kuang Wang
A 10 Gbase-LX4 receiver front end transimpedance amplifier and limiting amplifier. ISCAS (4) (2004)
Tai-Cheng Lee, Behzad Razavi
A stabilization technique for phase-locked frequency synthesizers. IEEE J. Solid State Circuits 38 (6) (2003)
Chih-Chun Tang, Chia-Hsin Wu, Kun-Hsien Li, Tai-Cheng Lee, Shen-Iuan Liu
CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90° delay network. ISCAS (3) (2002)
Tai-Cheng Lee, Behzad Razavi
A 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire. IEEE J. Solid State Circuits 36 (3) (2001)
Tai-Cheng Lee, Behzad Razavi
A 125-MHz CMOS mixed-signal equalizer for Gigabit Ethernet on copper wire. CICC (2001)
Tai-Cheng Lee, Behzad Razavi
A 4-tap 125-MHz mixed-signal echo canceller for Gigabit Ethernet on copper wire. CICC (2000)