Jau-Ji Jou

Publication Activity (10 Years)

Years Active: 2002-2023
Publications (10 Years): 13

Top Topics

Cmos Technology

Signal Acquisition

Top Venues

Publications

Chao-Ho Chen, Tsong-Yi Chen, Yong-Lin Chen, Bing-Hong Liu, Jau-Ji Jou, Cheng-Kang Wen
The Abnormal Events Detection System by Feature Enhancement-Based Deep Learning Network. GCCE (2023)
Vinh V. Le, Dung H. P. Nguyen, Bing-Hong Liu, Shao-I Chu, Chih-Yuan Lien, Jau-Ji Jou
An Algorithm Design for Minimum-Latency Scheduling in Multiple-Data-Type Multi-Channel WSNs. GCCE (2022)
C. L. Chiu, Ting-Rong Chen, Chia-Wei Lee, Jau-Ji Jou
The Study of 60 GHz Wideband Conductor-Backed Coplanar Waveguide on a TGV Substrate. GCCE (2022)
Jau-Ji Jou, Tien-Tsorng Shih, Hao-Wen Hsu
32-Gb/s NRZ and 40-Gb/s PAM-4 Transimpedance Amplifier Paralleling with a Differentiator for Bandwidth Enhancement in 90-nm CMOS Technology. Circuits Syst. Signal Process. 41 (2) (2022)
Chun-Chen Yao, Jun-Yuan Zheng, Jau-Ji Jou, Chun-Liang Yang
Performance Monitoring of High-Speed NRZ Signals Using Machine Learning Techniques. ISPACS (2021)
Hao-Wen Hsu, Xuan-Yi Ye, Jau-Ji Jou, Tien-Tsorng Shih
A 40-Gb/s NRZ Inductorless Transimpedance Amplifier in a 0.18-μm SiGe BiCMOS Technology. ISPACS (2021)
Jian-Yu Lai, Chuan-Yu Liao, Jau-Ji Jou, Tien-Tsorng Shih, Po-Jui Chiang
Design of High-Speed Optical Receiver Module for 160Gb/s NRZ and 200Gb/s PAM4 Transmissions. ISCAS (2019)
Tsung-Yen Wu, Jau-Ji Jou, Tien-Tsorng Shih, Po-Jui Chiang, Yaw-Dung Wu
Design of a 25-Gb/s PAM-4 VCSEL Diode Driver with an Equalizer in 90-nm CMOS Technology. ISCAS (2019)
Hao-Wen Hsu, Chih-Chen Peng, Jau-Ji Jou, Tien-Tsorng Shih, Yaw-Dung Wu, Shao-I Chu, Chih-Yuan Lien, Bing-Hong Liu
25 Gb/s NRZ and 50 Gb/s PAM-4 Transimpedance Amplifier with Active Feedback and Equalization in 90 nm CMOS Technology. ICETE (1) (2019)
Chi-Hsien Wu, Jau-Ji Jou, Hsin-Wen Ting, Shao-I Chu, Bing-Hong Liu
Multi-channel multi-gigabit PRBS generator with a built-in clock in 0.18-μm CMOS technology. ISOCC (2017)
Chih-Chen Peng, Jau-Ji Jou, Tien-Tsorng Shih, Chien-Liang Chiu
High linearity transimpedance amplifier in 0.18-μm CMOS technology for 20-Gb/s PAM-4 receivers. ISOCC (2017)
Hsuan-Yun Kao, Cheng-Ting Tsai, Chun-Yen Pong, Shan-Fong Liang, Zu-Kai Weng, Yu-Chieh Chi, Hao-Chung Kuo, Jian Jang Huang, Tai-Cheng Lee, Tien-Tsorng Shih, Jau-Ji Jou, Wood-Hi Cheng, Chao-Hsin Wu, Gong-Ru Lin
Few-mode 850-nm VCSEL chip with direct 16-QAM OFDM encoding at 80-Gbit/s for 100-m OM4 MMF link. OFC (2017)
Hong-Jhih Chen, Jau-Ji Jou, Tien-Tsorng Shih
Design of pseudo-random bit sequence generator with adjustable sinusoidal jitter. ISOCC (2016)
Jau-Ji Jou, Cheng-Kuang Liu
Application of SPICE simulation to study WDM and SCM systems using EDFAs with chirping. IEEE Trans. Educ. 45 (3) (2002)