Login / Signup
Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks.
Po-Tsang Huang
Wei Hwang
Published in:
IEICE Trans. Fundam. Electron. Commun. Comput. Sci. (2011)
Keyphrases
</>
high speed
low cost
interconnection networks
real time
web services
digital libraries