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A 38.64-Gb/s Large-CPM 2-KB LDPC Decoder Implementation for nand Flash Memories.

Li-Wei LiuMu-Hua YuanYen-Chin LiaoHsie-Chia Chang
Published in: IEEE Open J. Circuits Syst. (2022)
Keyphrases
  • ldpc codes
  • low density parity check
  • knowledge base
  • high speed
  • message passing
  • hardware implementation
  • decoding algorithm
  • fpga implementation
  • distributed source coding