Yung-Hui Chung

Publication Activity (10 Years)

Years Active: 2010-2024
Publications (10 Years): 29

Top Topics

Error Reduction

Cmos Image Sensor

Top Venues

IEEE Trans. Very Large Scale Integr. Syst.

IEEE Trans. Circuits Syst. I Regul. Pap.

Publications

Wei-Chung Lin, Yung-Chi Chang, Yung-Hui Chung
A 10b 400MS/s 2x-Time-Interleaved 2-Then-1b/Cycle SAR ADC in 90nm CMOS. ISCAS (2024)
Qi-Fen Zeng, Chia-Hui Tien, Yung-Hui Chung
A 105-dB SFDR 16-bit SAR ADC with a Window Capacitor Calibration Scheme. ISCAS (2024)
Hou-Hsuan Lin, Jia-Fong Shih, Yung-Hui Chung
A 90-dB DR Discrete-Time Delta-Sigma Modulator for Audio Applications. ISOCC (2023)
Yung-Hui Chung, Chia-Hui Tien, Qi-Feng Zeng
A 16-Bit Calibration-Free SAR ADC With Binary-Window and Capacitor-Swapping DAC Switching Schemes. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (1) (2022)
Bo-Wei Chen, Yung-Hui Chung, Chia-Ming Tsai
An 8-Bit 1.25-GS/s 2.5-GHz ERBW Folding-Subrange ADC with Power-Efficient Metastability Error Reduction Technique. VLSI-DAT (2021)
Yung-Hui Chung, Jia-Fong Shih, Yu-Hsiang Wang
A Resistor-Less CMOS Bandgap Reference with High-Order Temperature Compensation. APCCAS (2021)
Yung-Hui Chung, Qi-Feng Zeng, Yi-Shen Lin
A 12-bit SAR ADC With a DAC-Configurable Window Switching Scheme. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2020)
Yung-Hui Chung, Wei-Shu Rih
A 3-mW 12b 160-MS/s 2-Way Time-Interleaved Subrange SAR ADC in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (4) (2020)
Yung-Hui Chung, Qi-Feng Zeng
A 12-bit 100-kS/s SAR ADC for IoT Applications. VLSI-DAT (2020)
Yung-Hui Chung, Ya-Mien Hsu
A 12-Bit 100-MS/s Subrange SAR ADC With a Foreground Offset Tracking Calibration Scheme. IEEE Trans. Circuits Syst. II Express Briefs (7) (2019)
Yung-Hui Chung
A 12-bit Domino ADC with a Background Offset Calibration Scheme. APCCAS (2019)
Yung-Hui Chung, Min-Sheng Chiang
A 12-Bit Synchronous-SAR ADC for IoT Applications. ISCAS (2019)
Yung-Hui Chung, Chia-Hui Tien, Qi-Feng Zeng
A 102dB-SFDR 16-bit Calibration-Free SAR ADC in 180-nm CMOS. APCCAS (2019)
Yung-Hui Chung, Wei-Shu Rih, Che-Wei Chang
A 6-bit 1.3-GS/s Ping-Pong Domino-SAR ADC in 55-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs (8) (2018)
Yung-Hui Chung, Chia-Wei Yen, Pei-Kang Tsai, Bo-Wei Chen
A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme. IEEE Trans. Very Large Scale Integr. Syst. 26 (10) (2018)
Yung-Hui Chung, Yi-Shen Lin, Qi-Feng Zeng
A 12-bit 20-MS/s SAR ADC With Fast-Binary-Window DAC Switching in 180nm CMOS. APCCAS (2018)
Yung-Hui Chung, Chia-Wei Yen, Pei-Kang Tsai
A 12-bit 10-MS/s SAR ADC with a binary-window DAC switching scheme in 180-nm CMOS. Int. J. Circuit Theory Appl. 46 (4) (2018)
Yung-Hui Chung, Chia-Yi Hu, Che-Wei Chang
A 38-mW 7-bit 5-GS/s Time-Interleaved SAR ADC with Background Skew Calibration. A-SSCC (2018)
Yung-Hui Chung, Wei-Shu Rih
A 6-bit 1.6-GS/s domino-SAR ADC in 55nm CMOS. ISOCC (2017)
Yung-Hui Chung, Song-You Shih
A 10-bit 100-MS/s SAR ADC with capacitor swapping technique in 90-nm CMOS. VLSI-DAT (2017)
Yung-Hui Chung, Chia-Wei Yen
An 11-bit 100-MS/s Subranged-SAR ADC in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 25 (12) (2017)
Yung-Hui Chung, Ya-Mien Hsu, Chia-Wei Yen, Wei-Shu Rih
A 12-bit 160-MS/s ping-pong subranged-SAR ADC in 65nm CMOS. ISOCC (2017)
Yung-Hui Chung, Cheng-Hsun Tsai, Hsuan-Chih Yeh
A 5-bit 1-GS/s binary-search ADC in 90-nm CMOS. Microelectron. J. 63 (2017)
Yung-Hui Chung, Chia-Wei Yen
A PVT-tracking metastability detector for asynchronous ADCs. ISCAS (2016)
Yung-Hui Chung, Cheng-Hsun Tsai, Hsuan-Chih Yeh
A 5-b 1-GS/s binary-search ADC in 90nm CMOS. APCCAS (2016)
Yung-Hui Chung, Chia-Wei Yen, Meng-Hsuan Wu
A 24- μW 12-bit 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 24 (11) (2016)
Yung-Hui Chung, Cheng-Hsun Tsai, Hsuan-Chin Yeh
A 5-b 1-GS/s 2.7-mW binary-search ADC in 90nm digital CMOS. SoCC (2015)
Yung-Hui Chung, Jieh-Tsorng Wu
A 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 23 (3) (2015)
Yung-Hui Chung, Meng-Hsuan Wu, Hung-Sung Li
A 12-bit 8.47-fJ/Conversion-Step Capacitor-Swapping SAR ADC in 110-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2015)
Yung-Hui Chung
Perturbation-based digital background calibration technique for pipelined ADCs. ISCAS (2014)
Yung-Hui Chung
The swapping binary-window DAC switching technique for SAR ADCs. ISCAS (2013)
Yung-Hui Chung, Meng-Hsuan Wu, Hung-Sung Li
A 24μW 12b 1MS/s 68.3dB SNDR SAR ADC with two-step decision DAC switching. CICC (2013)
Yung-Hui Chung, Jieh-Tsorng Wu
A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC. IEEE J. Solid State Circuits 45 (11) (2010)