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An 8-Bit 1.25-GS/s 2.5-GHz ERBW Folding-Subrange ADC with Power-Efficient Metastability Error Reduction Technique.
Bo-Wei Chen
Yung-Hui Chung
Chia-Ming Tsai
Published in:
VLSI-DAT (2021)
Keyphrases
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error reduction
power consumption
data mining
semi supervised
pairwise