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Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell.

Jared L. ZerbeCarl W. WernerVladimir StojanovicFred ChenJason WeiGrace TsangDennis KimWilliam F. StonecypherAndrew HoTimothy P. ThrushRavi T. KolliparaMark A. HorowitzKevin S. Donnelly
Published in: IEEE J. Solid State Circuits (2003)
Keyphrases
  • high speed
  • neural network
  • learning algorithm
  • artificial intelligence
  • low power
  • multipath