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1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus.

Jared L. ZerbePak Shing ChauCarl W. WernerTimothy P. ThrushH. J. LiawBruno W. GarleppKevin S. Donnelly
Published in: IEEE J. Solid State Circuits (2001)
Keyphrases
  • high speed
  • low power
  • real time
  • analog circuits
  • shift register
  • learning algorithm
  • data acquisition
  • focal plane
  • data mining
  • information retrieval
  • decision trees
  • image sequences
  • multiscale
  • asynchronous circuits