A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips.
Ramin Farjad-RadWilliam J. DallyHiok-Tiaq NgRamesh SenthinathanMing-Ju Edward LeeRohit RathiJohn PoultonPublished in: IEEE J. Solid State Circuits (2002)
Keyphrases
- low power
- high speed
- power consumption
- mixed signal
- low power consumption
- vlsi circuits
- high power
- low cost
- single chip
- wireless transmission
- cmos image sensor
- real time
- logic circuits
- vlsi architecture
- power reduction
- frame rate
- packet loss
- gate array
- power saving
- delay insensitive
- circuit design
- image sensor
- high density
- motion estimation