Hiok-Tiaq Ng

Publication Activity (10 Years)

Years Active: 1997-2012
Publications (10 Years): 0

Top Venues

IEEE J. Solid State Circuits

Publications

Ramin Farjad-Rad, Friedel Gerfers, Michael Brown, Ahmad Tavakoli, David Nguyen, Hossein Sedarat, Ramin Shirani, Hiok-Tiaq Ng
A 48-Port FCC-Compliant 10GBASE-T Transmitter With Mixed-Mode Adaptive Echo Canceller. IEEE J. Solid State Circuits 47 (12) (2012)
Friedel Gerfers, Ramin Farjad-Rad, Michael Brown, Ahmad Tavakoli, David Nguyen, Hiok-Tiaq Ng, Ramin Shirani
A 16-port FCC-compliant 10GBase-T transmitter and hybrid with 76dBc SFDR up to 400MHz scalable to 48 ports. ISSCC (2012)
Ramin Farjad-Rad, Anhtuyet Nguyen, James Tran, Trey Greer, John Poulton, William J. Dally, John H. Edmondson, Ramesh Senthinathan, Rohit Rathi, Ming-Ju Edward Lee, Hiok-Tiaq Ng
A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. IEEE J. Solid State Circuits 39 (9) (2004)
Ming-Ju Edward Lee, William J. Dally, Trey Greer, Hiok-Tiaq Ng, Ramin Farjad-Rad, John Poulton, Ramesh Senthinathan
Jitter transfer characteristics of delay-locked loops - theories and design techniques. IEEE J. Solid State Circuits 38 (4) (2003)
Hiok-Tiaq Ng, M.-J. Edward Lee, Ramin Farjad-Rad, Ramesh Senthinathan, William J. Dally, Anhtuyet Nguyen, Rohit Rathi, Trey Greer, John Poulton, John H. Edmondson, James Tran
A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. CICC (2003)
M.-J. Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John W. Poulton
CMOS High-Speed I/Os - Present and Future. ICCD (2003)
Hiok-Tiaq Ng, Ramin Farjad-Rad, Ming-Ju Edward Lee, William J. Dally, Trey Greer, John Poulton, John H. Edmondson, Rohit Rathi, Ramesh Senthinathan
A second-order semidigital clock recovery circuit based on injection locking. IEEE J. Solid State Circuits 38 (12) (2003)
Ramin Farjad-Rad, William J. Dally, Hiok-Tiaq Ng, Ramesh Senthinathan, Ming-Ju Edward Lee, Rohit Rathi, John Poulton
A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips. IEEE J. Solid State Circuits 37 (12) (2002)
Hiok-Tiaq Ng, Ramsin M. Ziazadeh, David J. Allstot
A multistage amplifier technique with embedded frequency compensation. IEEE J. Solid State Circuits 34 (3) (1999)
Ramsin M. Ziazadeh, Hiok-Tiaq Ng, David J. Allstot
A multistage amplifier topology with embedded tracking compensation. CICC (1998)
Hiok-Tiaq Ng, David J. Allstot
CMOS current steering logic for low-voltage mixed-signal integrated circuits. IEEE Trans. Very Large Scale Integr. Syst. 5 (3) (1997)