Aida Varzaghani

Publication Activity (10 Years)

Years Active: 2006-2022
Publications (10 Years): 2

Top Topics

Representation Scheme

Logical Operations

Analog To Digital Converter

Top Venues

VLSI Technology and Circuits

IEEE J. Solid State Circuits

Publications

Aida Varzaghani, Bardia Bozorgzadeh, Jack Lam, Ankush Goel, Xiaobin Yuan, Mohamed Elzeftawi, Mehran Izad, Sudipta Sarkar, Alberto Baldisserotto, Seong-Ryong Ryu, Steven Mikes, Jeffrey Hwang, Varun Joshi, Shahrzad Naraghi, Darshan Kadia, Mohammad Ranjbar, Paul Lee, Dimitri Loizos, Sotirios Zogopoulos, Shwetabh Verma, Stefanos Sidiropoulos
A 1-to-112Gb/s DSP-Based Wireline Transceiver with a Flexible Clocking Scheme in 5nm FinFET. VLSI Technology and Circuits (2022)
Bharath Raghavan, Aida Varzaghani, Lakshmi P. Rao, Henry Park, Xiaochen Yang, Zhi Huang, Yu Chen, Rama Kattamuri, Chunhui Wu, Bo Zhang, Jun Cao, Afshin Momtaz, Namik Kocaman
A 125 mW 8.5-11.5 Gb/s serial link transceiver with a dual path 6-bit ADC/5-tap DFE receiver and a 4-tap FFE transmitter in 28 nm CMOS. VLSI Circuits (2016)
Aida Varzaghani, Athos Kasapi, Dimitri Loizos, Song-Hee Paik, Shwetabh Verma, Sotirios Zogopoulos, Stefanos Sidiropoulos
A 10.3-GS/s, 6-Bit Flash ADC for 10G Ethernet Applications. IEEE J. Solid State Circuits 48 (12) (2013)
Shwetabh Verma, Athos Kasapi, Li-min Lee, Dean Liu, Dimitri Loizos, Song-Hee Paik, Aida Varzaghani, Sotirios Zogopoulos, Stefanos Sidiropoulos
A 10.3GS/s 6b flash ADC for 10G Ethernet applications. ISSCC (2013)
Aida Varzaghani, Chih-Kong Ken Yang
A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization. IEEE J. Solid State Circuits 44 (3) (2009)
Azita Emami-Neyestanak, Aida Varzaghani, John F. Bulzacchelli, Alexander V. Rylyakov, Chih-Kong Ken Yang, Daniel J. Friedman
A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE. IEEE J. Solid State Circuits 42 (4) (2007)
Aida Varzaghani, Chih-Kong Ken Yang
A 6-GSamples/s multi-level decision feedback equalizer embedded in a 4-bit time-interleaved pipeline A/D converter. IEEE J. Solid State Circuits 41 (4) (2006)
Aida Varzaghani, Chih-Kong Ken Yang
A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration. IEEE J. Solid State Circuits 41 (2) (2006)