A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS.
Liangxiao TangWeixin GaiChih-Kong Ken YangBingyi YeCongcong ChenPublished in: ISCAS (2021)
Keyphrases
- power consumption
- high speed
- low power
- nm technology
- adaptive sampling
- cmos technology
- decision feedback
- power supply
- monte carlo
- optimization problems
- hd video
- optimization algorithm
- power reduction
- random sampling
- sample size
- low cost
- parallel processing
- power dissipation
- objective function
- optimization method
- infrared
- motion estimation