Ming-Shuan Chen

Publication Activity (10 Years)

Years Active: 2008-2015
Publications (10 Years): 3

Top Topics

Cmos Technology

Power Dissipation

Framework For Image Segmentation

Top Venues

IEEE J. Solid State Circuits

Publications

Amr Amin Hafez, Ming-Shuan Chen, Chih-Kong Ken Yang
A 32-48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology. IEEE J. Solid State Circuits 50 (3) (2015)
Ming-Shuan Chen, Chih-Kong Ken Yang
A 50-64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology. IEEE J. Solid State Circuits 50 (8) (2015)
Ming-Shuan Chen, Mau-Chung Frank Chang, Chih-Kong Ken Yang
A low-PDP and low-area repeater using passive CTLE for on-chip interconnects. VLSIC (2015)
Ming-Shuan Chen, Chih-Kong Ken Yang
A 50-64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65-nm CMOS. CICC (2014)
Ming-Shuan Chen, Amr Amin Hafez, Chih-Kong Ken Yang
A 0.1-1.5 GHz 8-bit Inverter-Based Digital-to-Phase Converter Using Harmonic Rejection. IEEE J. Solid State Circuits 48 (11) (2013)
Amr Amin Hafez, Ming-Shuan Chen, Chih-Kong Ken Yang
A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOS. ISSCC (2013)
Ming-Shuan Chen, Chih-Kong Ken Yang
A low-power highly multiplexed parallel PRBS generator. CICC (2012)
Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee
A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology. IEEE J. Solid State Circuits 47 (3) (2012)
Ming-Shuan Chen, Yu-Nan Shih, Chen-Lun Lin, Hao-Wei Hung, Jri Lee
A 40Gb/s TX and RX chip set in 65nm CMOS. ISSCC (2011)
Jri Lee, Ming-Shuan Chen, Huaide Wang
Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data. IEEE J. Solid State Circuits 43 (9) (2008)
Jri Lee, Ming-Shuan Chen, Huaide Wang
A 20Gb/s Duobinary Transceiver in 90nm CMOS. ISSCC (2008)