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A 50-64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology.
Ming-Shuan Chen
Chih-Kong Ken Yang
Published in:
IEEE J. Solid State Circuits (2015)
Keyphrases
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cmos technology
low power
high speed
spl times
power consumption
low voltage
parallel processing
low cost
image sensor
power dissipation
mixed signal
silicon on insulator
real time
pattern recognition
camera motion
multi channel