A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation.
Mozhgan MansuriChih-Kong Ken YangPublished in: IEEE J. Solid State Circuits (2003)
Keyphrases
- low power
- power consumption
- high speed
- energy dissipation
- low cost
- buffer size
- single chip
- high power
- clock frequency
- low power consumption
- vlsi circuits
- mixed signal
- logic circuits
- digital signal processing
- power reduction
- noise model
- wireless transmission
- cmos technology
- vlsi architecture
- image processing
- power dissipation
- signal to noise ratio
- gaussian noise
- signal processor
- ultra low power