Paul J. Hurst

Publication Activity (10 Years)

Years Active: 1988-2022
Publications (10 Years): 6

Top Topics

Original Signal

Statistical Approaches

Geometric Properties

Top Venues

IEEE Trans. Circuits Syst. I Regul. Pap.

IEEE J. Solid State Circuits

IEEE Trans. Circuits Syst. II Express Briefs

Publications

Christopher K. Su, Paul J. Hurst, Stephen H. Lewis
A Time-Interleaved SAR ADC With Signal-Independent Background Timing Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. 69 (2) (2022)
Yi-Long Yu, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
A Two-Step ADC With Statistical Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2020)
David J. Stoops, Jenny Kuo, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
Digital Background Calibration of a Split Current-Steering DAC. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2019)
Natalie S. Killeen, Duy P. Nguyen, Alexander N. Stameroff, Anh-Vu Pham, Paul J. Hurst
Design of a Wideband Bandpass Stacked HBT Distributed Amplifier in InP. ISCAS (2018)
Timothy A. Monk, Paul J. Hurst, Stephen H. Lewis
Iterative Gain Enhancement in an Algorithmic ADC. IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2016)
Mo M. Zhang, Paul J. Hurst, Stephen H. Lewis
An algorithmic ADC with greater than rail-to-rail input range and near-Vt supply. ISCAS (2016)
Dong Wang, John P. Keane, Paul J. Hurst, Stephen H. Lewis
An Integrator-Based Pipelined ADC With Digital Calibration. IEEE Trans. Circuits Syst. II Express Briefs (9) (2015)
Nick C.-J. Chang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
Background Adaptive Cancellation of Digital Switching Noise in a Pipelined Analog-to-Digital Converter Without Noise Sensors. IEEE J. Solid State Circuits 49 (6) (2014)
Omar A. Hafiz, Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis
Immediate Calibration of Operational Amplifier Gain Error in Pipelined ADCs Using Extended Correlated Double Sampling. IEEE J. Solid State Circuits 48 (3) (2013)
Lakshmi P. Rao, Nattapol Sitthimahachaikul, Paul J. Hurst
Correcting the Effects of Mismatches in Time-Interleaved Analog Adaptive FIR Equalizers. IEEE Trans. Circuits Syst. I Regul. Pap. (11) (2012)
Nick C.-J. Chang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
Background adaptive cancellation of digital switching noise in pipelined ADCs without noise sensors. CICC (2012)
Nattapol Sitthimahachaikul, Lakshmi P. Rao, Paul J. Hurst
Canceling the ISI Due to Finite S/H Bandwidth in a Circular Buffer Forward Equalizer. IEEE Trans. Circuits Syst. II Express Briefs (3) (2012)
Nattapol Sitthimahachaikul, Lakshmi P. Rao, Paul J. Hurst
Overcoming the Effect of the Summation-Node Parasitic Pole in an Analog Equalizer. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2012)
Shankar Guhados, Paul J. Hurst, Stephen H. Lewis
Errors/Sample. IEEE J. Solid State Circuits 47 (9) (2012)
Kerry A. O'Donoghue, Paul J. Hurst, Stephen H. Lewis
A Digitally Corrected 5-mW 2-MS/s SC Delta Sigma ADC in 0.25- μ m CMOS With 94-dB SFDR. IEEE J. Solid State Circuits 46 (11) (2011)
Oliver E. Gysel, Paul J. Hurst, Stephen H. Lewis
Highly programmable switched-capacitor filters using biquads with nonuniform internal clocks. SoCC (2010)
Mo M. Zhang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
Calibration of pipelined ADC gain and memory errors in an adaptively equalized receiver. ISCAS (2010)
Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst
A parametric polyphase domain approach to blind calibration of timing mismatches for M-channel time-interleaved ADCs. ISCAS (2010)
Kerry A. O'Donoghue, Paul J. Hurst, Stephen H. Lewis
A digitally calibrated 5-mW 2-MS/s 4th-order ΔΣ ADC in 0.25-μm CMOS with 94 dB SFDR. ESSCIRC (2010)
Chi Ho Law, Paul J. Hurst, Stephen H. Lewis
A Four-Channel Time-Interleaved ADC With Digital Calibration of Interchannel Timing and Memory Errors. IEEE J. Solid State Circuits 45 (10) (2010)
Tunde Wang, Dong Wang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
A Level-Crossing Analog-to-Digital Converter With Triangular Dither. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2009)
Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst
Digital Calibration of a Nonlinear S/H. IEEE J. Sel. Top. Signal Process. 3 (3) (2009)
Mo M. Zhang, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
Gain-Error Calibration of a Pipelined ADC in an Adaptively Equalized Baseband Receiver. IEEE Trans. Circuits Syst. II Express Briefs (10) (2009)
Haoyue Wang, Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis
Nested Digital Background Calibration of a 12-bit Pipelined ADC Without an Input SHA. IEEE J. Solid State Circuits 44 (10) (2009)
Tsung-Heng Tsai, Paul J. Hurst, Stephen H. Lewis
Correction of Mismatches in a Time-Interleaved Analog-to-Digital Converter in an Adaptively Equalized Digital Communication Receiver. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2009)
Nathaniel J. Guilar, Rajeevan Amirtharajah, Paul J. Hurst
A Full-Wave Rectifier With Integrated Peak Selection for Multiple Electrode Piezoelectric Energy Harvesters. IEEE J. Solid State Circuits 44 (1) (2009)
Nathaniel J. Guilar, Rajeevan Amirtharajah, Paul J. Hurst, Stephen H. Lewis
An energy-aware multiple-input power supply with charge recovery for energy harvesting applications. ISSCC (2009)
Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst
Adaptive Semiblind Calibration of Bandwidth Mismatch for Two-Channel Time-Interleaved ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. (9) (2009)
Nathaniel J. Guilar, Rajeevan Amirtharajah, Paul J. Hurst
A Full-Wave Rectifier for Interfacing with Multi-Phase Piezoelectric Energy Harvesters. ISSCC (2008)
Paul J. Hurst, Andy Norrell
DAC Quantization-Noise Cancellation in an Echo-Canceling Transceiver. IEEE Trans. Circuits Syst. II Express Briefs (2) (2008)
Russell A. Hershbarger, Wenyan Jia, Kiam M. Tey, Kiyoshi Fukahori, Paul J. Hurst, Manprit Kapoor
A Programmable Impedance Matching Circuit for Voiceband Modems. IEEE J. Solid State Circuits 43 (2) (2008)
Patrick Satarzadeh, Bernard C. Levy, Paul J. Hurst
Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved A/D Converter. ISCAS (2007)
Nathaniel J. Guilar, Frank Lau, Paul J. Hurst, Stephen H. Lewis
A Passive Switched-Capacitor Finite-Impulse-Response Equalizer. IEEE J. Solid State Circuits 42 (2) (2007)
Mo M. Zhang, Paul J. Hurst
Effect of nonlinearity in the CMFB circuit that uses the differential-difference amplifier. ISCAS (2006)
Tsung-Heng Tsai, Paul J. Hurst, Stephen H. Lewis
Bandwidth Mismatch and Its Correction in Time-Interleaved Analog-to-Digital Converters. IEEE Trans. Circuits Syst. II Express Briefs (10) (2006)
John P. Keane, Paul J. Hurst, Stephen H. Lewis
Digital background calibration for memory effects in pipelined analog-to-digital converters. IEEE Trans. Circuits Syst. I Regul. Pap. (3) (2006)
Dong Wang, John P. Keane, Paul J. Hurst, Bernard C. Levy, Stephen H. Lewis
Convergence analysis of a background interstage gain calibration technique for pipelined ADCs. ISCAS (4) (2005)
John P. Keane, Paul J. Hurst, Stephen H. Lewis
Background interstage gain calibration technique for pipelined ADCs. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2005)
Shafiq M. Jamal, Daihong Fu, Mahendra P. Singh, Paul J. Hurst, Stephen H. Lewis
Correction to "Calibration of Sample-Time Error in a Two-Channel Time-Interleaved Analog-to-Digital Converter". IEEE Trans. Circuits Syst. I Regul. Pap. (4) (2005)
Nathaniel J. Guilar, Pak-Kim Lau, Paul J. Hurst, Stephen H. Lewis
A 200 MS/s passive switched-capacitor FIR equalizer using a time-interleaved topology. CICC (2005)
Carl R. Grace, Paul J. Hurst, Stephen H. Lewis
A 12-bit 80-MSample/s pipelined ADC with bootstrapped digital calibration. IEEE J. Solid State Circuits 40 (5) (2005)
Anthony Tong, Paul J. Hurst
A mixed-signal approach for tuning continuous-time low-pass filters. IEEE Trans. Circuits Syst. II Express Briefs (6) (2004)
Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis
A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration. IEEE J. Solid State Circuits 39 (11) (2004)
Shafiq M. Jamal, Daihong Fu, Mahendra P. Singh, Paul J. Hurst, Stephen H. Lewis
Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter. IEEE Trans. Circuits Syst. I Regul. Pap. (1) (2004)
Ryan S. Prendergast, Bernard C. Levy, Paul J. Hurst
Reconstruction of band-limited periodic nonuniformly sampled signals through multirate filter banks. IEEE Trans. Circuits Syst. I Regul. Pap. (8) (2004)
Paul J. Hurst, Stephen H. Lewis, John P. Keane, Farbod Aram, Kenneth C. Dyer
Miller compensation using current buffers in fully differential CMOS two-stage operational amplifiers. IEEE Trans. Circuits Syst. I Regul. Pap. (2) (2004)
Eric B. Blecker, Thomas M. McDonald, Ozan E. Erdogan, Paul J. Hurst, Stephen H. Lewis
Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue. IEEE J. Solid State Circuits 38 (6) (2003)
John P. Keane, Michael Q. Le, Paul J. Hurst
Analog timing recovery for a noise-predictive decision-feedback equalizer. IEEE J. Solid State Circuits 38 (2) (2003)
Xiaoyue Wang, Paul J. Hurst, Stephen H. Lewis
A 12-bit 20-MS/s pipelined ADC with nested digital background calibration. CICC (2003)
Michael Q. Le, Paul J. Hurst, John P. Keane
An adaptive analog noise-predictive decision-feedback equalizer. IEEE J. Solid State Circuits 37 (2) (2002)
Shafiq M. Jamal, Daihong Fu, Nick C.-J. Chang, Paul J. Hurst, Stephen H. Lewis
A 10-b 120-Msample/s time-interleaved analog-to-digital converter with digital background calibration. IEEE J. Solid State Circuits 37 (12) (2002)
Anthony Tong, Paul J. Hurst
A mixed-signal tuning approach for continuous-time LPFs. ISCAS (1) (2001)
Amit Gattani, David W. Cline, Paul J. Hurst, Paul M. Mosinskis
A CMOS HDSL2 analog front-end. IEEE J. Solid State Circuits 35 (12) (2000)
Pierte Roo, Richard R. Spencer, Paul J. Hurst
A CMOS analog timing recovery circuit for PRML detectors. IEEE J. Solid State Circuits 35 (1) (2000)
Ozan E. Erdogan, Paul J. Hurst, Stephen H. Lewis
A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD. IEEE J. Solid State Circuits 34 (12) (1999)
Michael Q. Le, Paul J. Hurst, Kenneth C. Dyer
An analog DFE for disk drives using a mixed-signal integrator. IEEE J. Solid State Circuits 34 (5) (1999)
Daihong Fu, Kenneth C. Dyer, Stephen H. Lewis, Paul J. Hurst
A digital background calibration technique for time-interleaved analog-to-digital converters. IEEE J. Solid State Circuits 33 (12) (1998)
Kenneth C. Dyer, Daihong Fu, Stephen H. Lewis, Paul J. Hurst
An analog background calibration technique for time-interleaved analog-to-digital converters. IEEE J. Solid State Circuits 33 (12) (1998)
Tanchu Shih, Lawrence Der, Stephen H. Lewis, Paul J. Hurst
A fully differential comparator using a switched-capacitor differencing circuit with common-mode rejection. IEEE J. Solid State Circuits 32 (2) (1997)
Chuc K. Thanh, Stephen H. Lewis, Paul J. Hurst
A second-order double-sampled delta-sigma modulator using individual-level averaging. IEEE J. Solid State Circuits 32 (8) (1997)
Ravinder S. Kajley, Paul J. Hurst, James E. C. Brown
A mixed-signal decision-feedback equalizer that uses a look-ahead architecture. IEEE J. Solid State Circuits 32 (3) (1997)
Bret C. Rothenberg, James E. C. Brown, Paul J. Hurst, Stephen H. Lewis
A mixed-signal RAM decision-feedback equalizer for disk drives. IEEE J. Solid State Circuits 32 (5) (1997)
James E. C. Brown, Paul J. Hurst, Lawrence Der
A 35 Mb/s mixed-signal decision-feedback equalizer for disk drives in 2-μm CMOS. IEEE J. Solid State Circuits 31 (9) (1996)
Ted Vinko Burmas, Kenneth C. Dyer, Paul J. Hurst, Stephen H. Lewis
A second-order double-sampled delta-sigma modulator using additive-error switching. IEEE J. Solid State Circuits 31 (3) (1996)
Steven K. Berg, Paul J. Hurst, Stephen H. Lewis
An 80-Msample/s video switched-capacitor filter using a parallel biquadratic structure. IEEE J. Solid State Circuits 30 (8) (1995)
Paul J. Hurst, Bret C. Rothenberg
A programmable clock generator that uses noise shaping and its application in switched-capacitor filters. IEEE J. Solid State Circuits 30 (4) (1995)
Bret C. Rothenberg, Stephen H. Lewis, Paul J. Hurst
A 20-Msample/s switched-capacitor finite-impulse-response filter using a transposed structure. IEEE J. Solid State Circuits 30 (12) (1995)
James E. C. Brown, Paul J. Hurst, Lawrence Der, Iskender Agi
A Comparison of Analog DFE Architectures for Disk-Drive Applications. ISCAS (1994)
Eric Shieh, K. Wayne Current, Paul J. Hurst, Iskender Agi
High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architecture. IEEE Trans. Circuits Syst. Video Technol. 2 (4) (1992)
Iskender Agi, Paul J. Hurst, Anil K. Jain
A VLSI processor for parallel contour tracing. IEEE Trans. Signal Process. 40 (2) (1992)
Paul J. Hurst, K. Wayne Current, Iskender Agi, Eric Shieh
A VLSI architecture for two-dimensional Radon transform computations. ICASSP (1990)
K. Wayne Current, Paul J. Hurst, Eric Shieh, Iskender Agi
An evaluation of Radon transform computations using DSP chips. Mach. Vis. Appl. 3 (2) (1990)
Stephen Azevedo, James M. Brase, Harry E. Martz, Anil K. Jain, K. Wayne Current, Paul J. Hurst
A Radon transform computer for multidimensional signal processing. ICASSP (1989)
Iskender Agi, Paul J. Hurst, Anil K. Jain
An expandable VLSI processor array approach to contour tracing. ICASSP (1988)