Variable Input Delay CMOS Logic for Low Power Design.
Tezaswi RajaVishwani D. AgrawalMichael L. BushnellPublished in: VLSI Design (2005)
Keyphrases
- low power
- power dissipation
- logic circuits
- power consumption
- single chip
- high speed
- low cost
- vlsi architecture
- cmos technology
- chip design
- low power consumption
- delay insensitive
- ultra low power
- mixed signal
- digital signal processing
- gate array
- vlsi circuits
- image sensor
- power reduction
- cmos image sensor
- nm technology
- wireless transmission
- high power
- multi channel
- real time
- analog to digital converter
- design methodology
- signal processor