Variable Input Delay CMOS Logic for Low Power Design.
Tezaswi RajaVishwani D. AgrawalMichael L. BushnellPublished in: IEEE Trans. Very Large Scale Integr. Syst. (2009)
Keyphrases
- low power
- power dissipation
- logic circuits
- power consumption
- single chip
- cmos technology
- low cost
- high speed
- chip design
- low power consumption
- vlsi architecture
- digital signal processing
- delay insensitive
- vlsi circuits
- ultra low power
- cmos image sensor
- nm technology
- gate array
- image sensor
- power reduction
- mixed signal
- high power
- low voltage
- design process
- power management
- image processing
- wireless transmission
- circuit design