Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation.
Mandyam-Komar SrinivasMichael L. BushnellVishwani D. AgrawalPublished in: VLSI Design (1997)
Keyphrases
- test generation
- test cases
- symbolic execution
- test sequences
- fault diagnosis
- power dissipation
- quality assurance
- high speed
- static analysis
- short circuit
- software testing
- query language
- fault detection
- design automation
- path length
- mutation testing
- phase locked loop
- circuit design
- destination node
- shortest path
- test data generation
- data model
- neural network