A graph approach to DFT hardware placement for robust delay fault BIST.
Imtiaz P. ShaikMichael L. BushnellPublished in: VLSI Design (1995)
Keyphrases
- real time
- low cost
- random walk
- frequency domain
- fault diagnosis
- image processing
- graph representation
- directed graph
- graph structure
- graph based algorithm
- fault detection
- weighted graph
- graph theory
- hardware and software
- embedded systems
- partial occlusion
- computationally efficient
- computer systems
- pairwise
- neural network