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Automatic Path-Delay Fault Test Generation for Combined Resistive Vias, Resistive Bridges, and Capacitive Crosstalk Delay Faults.
Shweta Chary
Michael L. Bushnell
Published in:
VLSI Design (2006)
Keyphrases
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test generation
fault diagnosis
test cases
fault detection
high density
query processing
fault model
database
learning algorithm
artificial intelligence
decision trees
case study
error rate
complex systems
integrated circuit
error detection