A novel dynamic power cutoff technique (DPCT) for active leakage reduction in deep submicron CMOS circuits.
Baozhen YuMichael L. BushnellPublished in: ISLPED (2006)
Keyphrases
- vlsi circuits
- power consumption
- low power
- power dissipation
- power reduction
- delay insensitive
- clock gating
- high speed
- circuit design
- chip design
- analog vlsi
- dynamic environments
- data sets
- mixed signal
- ultra low power
- cmos technology
- data leakage prevention
- random access memory
- focal plane
- power management
- image processing