Siddharth Rao

Publication Activity (10 Years)

Years Active: 2017-2024
Publications (10 Years): 23

Top Topics

Special Session

Error Correction

Top Venues

Publications

Surendra Hemaram, Mehdi B. Tahoori, Francky Catthoor, Siddharth Rao, Sebastien Couet, Gouri Sankar Kar
Hard Error Correction in STT-MRAM. ASPDAC (2024)
Sicong Yuan, Mohammad Amin Yaldagard, Hanzhi Xun, Moritz Fieback, Erik Jan Marinissen, Woojin Kim, Siddharth Rao, Sebastien Couet, Mottaqiallah Taouil, Said Hamdioui
Design-for-Test for Intermittent Faults in STT-MRAMs. ETS (2024)
Ahmed Aouichi, Sicong Yuan, Moritz Fieback, Siddharth Rao, Woojin Kim, Erik Jan Marinissen, Sebastien Couet, Mottaqiallah Taouil, Said Hamdioui
Device Aware Diagnosis for Unique Defects in STT-MRAMs. ATS (2023)
Siddharth Rao, Kaiming Cai, Giacomo Talmelli, Nathali Franchina-Vergel, Ward Janssens, Hubert Hody, Farrukh Yasin, Kurt Wostyn, Sebastien Couet
Spin-orbit torque MRAM for ultrafast cache and neuromorphic computing applications. IMW (2023)
M. Gupta, Siddharth Rao, Gouri Sankar Kar, S. Couet
Magnetic Domain Wall Memory: A DTCO study for Memory Applications. ESSDERC (2023)
Simon Van Beek, Kaiming Cai, Kaiquan Fan, Giacomo Talmelli, Anna Trovato, Nico Jossart, Siddharth Rao, Adrian Vaisman Chasin, Sebastien Couet
MTJ degradation in multi-pillar SOT-MRAM with selective writing. IRPS (2023)
Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs. IEEE Trans. Computers 71 (9) (2022)
Kaiming Cai, Simon Van Beek, Siddharth Rao, K. Fan, M. Gupta, V. D. Nguyen, Ganesh Jayakumar, G. Talmelli, S. Couet, Gouri Sankar Kar
Selective operations of multi-pillar SOT-MRAM for high density and low power embedded memories. VLSI Technology and Circuits (2022)
Anteneh Gebregiorgis, Lizhou Wu, Christopher Münch, Siddharth Rao, Mehdi B. Tahoori, Said Hamdioui
Special Session: STT-MRAMs: Technology, Design and Test. VTS (2022)
Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41 (11) (2022)
Simon Van Beek, Kaiming Cai, Siddharth Rao, Ganesh Jayakumar, Sebastien Couet, Nico Jossart, Adrian Chasin, Gouri Sankar Kar
MTJ degradation in SOT-MRAM by self-heating-induced diffusion. IRPS (2022)
Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions. ITC (2021)
Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM. DATE (2021)
Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Guilherme Cardoso Medeiros, Moritz Fieback, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
Defect and Fault Modeling Framework for STT-MRAM Testing. IEEE Trans. Emerg. Top. Comput. 9 (2) (2021)
Simon Van Beek, Siddharth Rao, Shreya Kundu, Woojin Kim, Barry J. O'Sullivan, Stefan Cosemans, Farrukh Yasin, Robert Carpenter, Sebastien Couet, Shamin H. Sharifi, Nico Jossart, Davide Crotti, Gouri Sankar Kar
Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution. IRPS (2021)
Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
Impact of Magnetic Coupling and Density on STT-MRAM Performance. CoRR (2020)
Lizhou Wu, Mottaqiallah Taouil, Siddharth Rao, Erik Jan Marinissen, Said Hamdioui
Survey on STT-MRAM Testing: Failure Mechanisms, Fault Models, and Tests. CoRR (2020)
Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
Impact of Magnetic Coupling and Density on STT-MRAM Performance. DATE (2020)
Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui
Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs. ITC (2020)
Moritz Fieback, Lizhou Wu, Guilherme Cardoso Medeiros, Hassen Aziza, Siddharth Rao, Erik Jan Marinissen, Mottaqiallah Taouil, Said Hamdioui
Device-Aware Test: A New Test Approach Towards DPPB Level. ITC (2019)
Lizhou Wu, Siddharth Rao, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Erik Jan Marinissen, Farrukh Yasin, Sebastien Couet, Said Hamdioui, Gouri Sankar Kar
Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing. ETS (2019)
Lizhou Wu, Mottaqiallah Taouil, Siddharth Rao, Erik Jan Marinissen, Said Hamdioui
Electrical Modeling of STT-MRAM Defects. ITC (2018)
Manu Komalan, Sushil Sakhare, Trong Huynh Bao, Siddharth Rao, Woojin Kim, Christian Tenllado, José Ignacio Gómez, Gouri Sankar Kar, Arnaud Furnémont, Francky Catthoor
Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems. ISCAS (2017)